Год выпуска: 2010 Автор: Chandan Karfa,Dipankar Sarkar and Chittaranjan Mandal Издательство: LAP Lambert Academic Publishing Страниц: 204 ISBN: 9783838398136
Описание
Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go hand-in-hand with each phase of synthesis with scope to handle the special characteristics of each synthesis sub-task separately. This book is concerned with hand-in-hand verification and (high-level) synthesis of digital circuits. The verification problem is formulated as equivalence checking between two finite state machines with data-paths (FSMD). The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. A high-level synthesis tool, called structured architecture synthesis tool...
